In the fabrication of LDMOS power transistors as part of an integrated circuit manufacturing process, for performance and cost reasons, it is desirable for power transistors to be as small as possible. For cost reasons, it is also desirable to minimize the number of photomasking steps in the manufacturing process.
A prior art integrated LDMOS transistor is shown in cross-section in FIG. 1. Power LDMOS transistors are usually laid out in stripes with very large width with source and drain stripes alternating. The active area of the LDMOS is the product of the total width and the Halfpitch, which, the Halfpitch as shown in FIG. 1, is the distance between the center of the source stripe and the center of the drain stripe.
Heavily doped N+ and P+ regions are fabricated in the source stripes to contact the source and body, respectively. Under the N+ and P+ regions, there is a p-type shallow body region. The side-diffusion of this region under the gate polysilicon defines the channel of the LDMOS. The implants forming this region are shallow enough that the gate polysilicon could form an effective implant blocker, meaning that the shallow body region can be self-aligned to the polysilicon edge.
There also needs to be a p-type deep body region within the source stripe. This deep body region increases the radius of curvature of the body to drain junction and reduces the electrical resistance of the body region under the N+ source, thereby prevents the turn-on of a parasitic NPN transistor under high drain voltage conditions, which could cause device destruction.
Since the deep body implants must have a projected range of up to approximately 0.5 um, the gate polysilicon of the LDMOS, which is typically 0.1-0.3 um thick, is not enough to block the deep implants. Therefore the deep body region must be defined by its own photomasking step, using a photoresist layer at least 0.8 um thick. This photomasking step can be done either before the poly gate definition (as in the simplified process flow of FIG. 2a) or after poly gate definition (as in FIG. 2b). Either way, since the deep body and gate polysilicon are defined by two different masks, there will be a misalignment between them which varies from wafer to wafer and site to site on the same wafer. If the deep body implants overlap the poly gate, threshold voltage of the LDMOS will increase by an amount dependant on the overlap. To avoid large variation of threshold voltage, the deep body mask opening must be spaced inside the source opening by an amount larger than the side-diffusion of the deep implants plus the maximum misalignment between the masks. This increases the minimum size of the source/body region.
Another way to produce a device with acceptably low threshold voltage variation would be to overlap the deep body implants and the poly gate by an amount much larger than the maximum misalignment. This has the disadvantage of increasing the channel length and halfpitch of the device.
From the foregoing discussion it can be concluded that an invention which reduces the area of the source/body region (and hence the LDMOS) while not increasing the total number of photomasking steps would be useful to a manufacturer of power integrated circuits.